Suhaib Fahmy’s Publications.

Below you will find a list of publications by the Accelerated Connected Computing Lab at KAUST (and its predecessors) and links to download them. Note that they are provided here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders.

You can also view Prof. Fahmy’s Google Scholar Profile, DBLP Profile, and ORCID Profile, and publications on the Warwick repository, WRAP and KAUST Repository.

Peer-Reviewed Conference and Journal Papers

• Automatic Code-Generation for Accelerating Structured-Mesh-Based Explicit Numerical Solvers on FPGAs
  B. Thileepan, S. A. Fahmy, and G. R. Mudalige
  Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), November 2025 (To Appear).

• FPGAs Are the Hero In-Network Computing Needs
  S. A. Fahmy, Z. Yang, Y. Chen, Z. Istvan, G. Alonso, and M. Canini
  Proceedings of the ACM SIGOPS Asia-Pacific Workshop on Systems (APSys), Seoul, Korea, October 2025 (To Appear).

• A Dataflow Overlay for Monte Carlo Multi-Asset Option Pricing on AMD Versal AI Engines
  M. Bouaziz, M. Samet, and S. A. Fahmy
  ISC High Performance Research Paper Proceedings, Hamburg, Germany, June 2025.

• PRNGine: Massively Parallel Pseudo-Random Number Generation and Probability Distribution Approximations on AMD AI Engines
  M. Bouaziz and S. A. Fahmy
  Proceedings of the Parallel and Distributed Processing Symposium Workshops (IPDPSW) – Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA), Milan, Italy, June 2025, pp. 91–98.

• Benchmarking Floating Point Performance of Massively Parallel Dataflow Overlays on AMD Versal Compute Primitives
  M. Bouaziz and S. A. Fahmy
  Proceedings of the Parallel and Distributed Processing Symposium Workshops (IPDPSW) – Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA), Milan, Italy, June 2025, pp. 99–103.

• High Throughput Low Latency Network Intrusion Detection on FPGAs: A Raw Packet Approach
  M. A. Farooq, A. Rafique, S. A. Fahmy, and A. Arora
  Proceedings of the Parallel and Distributed Processing Symposium Workshops (IPDPSW) – Reconfigurable Architectures Workshop (RAW), Milan, Italy, June 2025, pp. 1199–1205.

• ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
  A. T. Sheikh, A. Shoker, S. A. Fahmy, and P. Esteves-Veríssimo IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 6, pp. 1751–1764, June 2025.

2024

• Resilient and Secure Programmable System-on-Chip Accelerator Offload
  I. P. Gouveia, A. T. Sheikh, A. Shoker, S. A. Fahmy, and P. Esteves-Veríssimo
  Proceedings of the International Symposium on Reliable Distributed Systems (SRDS), Charlotte, NC, September 2024, pp. 52–56.

• SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning
  A. Rebai, M. A. Ojewale, A. Ullah, M. Canini, and S. A. Fahmy
  Proceedings of the SIGCOMM Workshop on Networks for AI Computing (NAIC), Sydney, Australia, August 2024, pp. 61–68.

• Split DNN Inference for Exploiting Near-Edge Accelerators
  H. Liu, M. E. Fouda, A. M. Eltawil and S. A. Fahmy
  Proceedings of the IEEE International Conference on Edge Computing and Communications (EDGE), Shenzhen, China, July 2024, pp. 84–91.

• DONNA: Distributed Optimized Neural Network Allocation on CIM-based Heterogeneous Accelerators
  M. Alshams, K. Smagulova, S. A. Fahmy, M. E. Fouda, and A. M. Eltawil
  Proceedings of the IEEE International Conference on Edge Computing and Communications (EDGE), Shenzhen, China, July 2024, pp. 149–156.
  EDGE 2024 Best Student Paper Award Winner

• Neural Architecture Search for In-Memory Computing-Based Deep Learning Accelerators
  O. Krestinskaya, M. E. Fouda, H. Benmeziane, K. El Maghraoui, A. Sebastian, W. D. Lu, M. Lanza, H. Li, F. Kurdahi, S. A. Fahmy, A. M. Eltawil, and K. N. Salama
  Nature Reviews Electrical Engineering, vol. 1, pp. 374–390, June 2024.

• Low-cost SCADA/HMI with Tiny Machine Learning for Monitoring Indoor CO2 Concentration
  I. N. K. Wardana, J. W. Gardner, and S. A. Fahmy
  Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, Glasgow, UK, May 2024.

• High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs
  M. W. Hassan, H. Ltaief, and S. A. Fahmy
  Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Orlando, FL, May 2024, pp. 13–23.

• Collaborative Learning at the Edge for Air Pollution Prediction
  I. N. K. Wardana, J. W. Gardner, and S. A. Fahmy
  IEEE Transactions on Instrumentation and Measurement, vol. 73, 2024.

• The NAIL Accelerator Interface Layer for Low Latency FPGA Offload
  E. Grindley, T. Gray, J. Wilkinson, C. Vaux, A. Ardron, J. Deeley, A. Elliott, N. T. Sumithran, and S. A. Fahmy
  IEEE Access, vol. 12, pp. 155976–155989, 2024.

2023

• TinyML Models for a Low-Cost Air Quality Monitoring Device
  I. N. K. Wardana, J. W. Gardner, and S. A. Fahmy
  IEEE Sensors Letters, vol. 7, no. 11, November 2023.

• ZyPR: End-to-End Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge
  A. R. Bucknall and S. A. Fahmy
  ACM Transactions on Reconfigurable Technology and Systems, vol. 16, no. 3, pp. 34:1–34:33, September 2023.

• Signal Detection for Large MIMO Systems Using Sphere Decoding on FPGAs
  M. W. Hassan A. Dabah, H. Ltaief, and S. A. Fahmy
  Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), St. Petersburg, FL, May 2023, pp. 102–111.

• REFL: Resource-Efficient Federated Learning
  A. M. Abdelmoniem, A. N. Sahu, M. Canini, and S. A. Fahmy
  Proceedings of the European Conference on Computer Systems (EuroSys), Rome, Italy, May 2023, pp. 215–232.

• Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs
  L. Ioannou and S. A. Fahmy
  ACM Transactions on Reconfigurable Technology and Systems, vol. 16, no. 1, pp. 8:1–8:26, March 2023.

2022

• High Throughput Multidimensional Tridiagonal System Solvers on FPGAs
  K. Kamalakkannan, G. R. Mudalige, I. Z. Reguly, and S. A. Fahmy
  Proceedings of the ACM International Conference on Supercomputing (ICS), June 2022, pp. 19:1–19:12.

• Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation
  A. K. Jain, D. L. Maskell, and S. A. Fahmy
  IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 6, pp. 1478–1490, June 2022.

• FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL
  K. Kamalakkannan, G. R. Mudalige, I. Z. Reguly, and S. A. Fahmy
  Proceedings of the International Workshop on OpenCL (IWOCL), May 2022, pp. 19:1–19:11.

• Estimation of Missing Air Pollutant Data Using a Spatiotemporal Convolutional Autoencoder
  I. N. K. Wardana, J. W. Gardner, and S. A. Fahmy
  Neural Computing and Applications, vol. 32, pp. 16129–16154, May 2022.

2021

• Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs
  K. Herath, A. Prakash, S. A. Fahmy, and T. Srikanthan
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 40, no. 12, December 2021.

• StressBench: A Configurable Full System Network and I/O Benchmark Framework
  D. G. Chester, T. Groves, S. D. Hammond, T. Law, S. A. Wright, R. Smedley-Stevenson, S. A. Fahmy, G. R. Mudalige, S. A. Jarvis
  Proceedings of the IEEE High Performance Extreme Computing Conference, September 2021.
  HPEC 2021 Best Paper Award Winner

• Heterogeneous Communication Virtualisation for Distributed Embedded Applications
  T. Pham, S. Shreejith, S. Steinhorst, S. A. Fahmy and S. Chakraborty
  Proceedings of the Euromicro Conference on Digital System Design, September 2021.

• Optimum Battery Weight for Maximizing Available Energy in UAV-Enabled Wireless Communications
  Hua Yan, Shuang-Hua Yang, Yunfei Chen, Suhaib A. Fahmy
  IEEE Wireless Communications Letters, vol. 10, no. 7, pp. 1410–1413, July 2021.

• High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers
  K. Kamalavasan, G. R. Mudalige, I. Z. Reguly, and S. A. Fahmy
  Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), May 2021, pp. 1087-1096.

• Sit Here: Placing Virtual Machines Securely in Cloud Environments
  M. Aldawood, A. Jhumka, and S. A. Fahmy
  Proceedings of the International Conference on Cloud Computing and Services Science, April 2021, pp. 248–259.

• Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware
  A. R. Bucknall and S. A. Fahmy
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), February 2021, pp. 1616–1621.

• Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction
  I. N. K. Wardana, J. W. Gardner, and S. A. Fahmy
  Sensors, vol. 21, no. 4, 1064, February 2021.

2020

• Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+
  A. R. Bucknall, S. Shanker, and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), December 2020.

• Exploring Hardware Accelerator Offload for the Internet of Things
  R. A. Cooke and S. A. Fahmy
  it – Information Technology, vol. 62, no. 5-6, pp. 207–214, December 2020, De Gruyter.

• High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay
  X. Li, K. Vipin, D. L. Maskell, S. A. Fahmy, and A. K. Jain
  Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), October 2020.

• Characterizing Latency Overheads in the Deployment of FPGA Accelerators
  R. A. Cooke and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), September 2020.

• High Throughput Spatial Convolution Filters on FPGAs
  L. Ioannou, A. Al-Dujaili, and S. A. Fahmy
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, pp. 1392–1402, June 2020.

• Quantifying the Latency Benefits of Near-Edge and In-Network FPGA Acceleration
  R. A. Cooke and S. A. Fahmy
  Proceedings of the International Workshop on Edge Systems, Analytics and Networking (EdgeSys), Heraklion, Greece, April 2020, pp. 7–12.

• A Model for Distributed In-Network and Near-Edge Computing With Heterogeneous Hardware
  R. A. Cooke and S. A. Fahmy
  Future Generation Computer Systems, vol. 105, pp. 395–409, April 2020.

2019

• Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration
  L. Ioannou and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), Tianjin, China, December 2019, pp. 355–358.

• Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration
  A. R. Bucknall, S. Shreejith, and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), Tianjin, China, December 2019, pp. 259–262.

• Network Intrusion Detection Using Neural Networks on FPGA SoCs
  L. Ioannou and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September 2019, pp. 232–238

• The Power-Optimised Software Envelope
  S. I. Roberts, S. A. Wright, S. A. Fahmy, and S. A. Jarvis
  ACM Transactions on Architecture and Code Optimization, vol. 16, no. 3, pp. 21:1–21:27, June 2019.

2018

• Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs
  S. A. Fahmy
  Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, UK, August 2018, pp. 142–147.

• A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs
  S. Shreejith, Ryan A. Cooke, and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Dublin, Ireland, August 2018, pp. 186–190.

• FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications
  K. Vipin and S. A. Fahmy
  ACM Computing Surveys, vol. 51, no. 4, pp. 72:1–72:39, July 2018.

• Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators
  S. Shreejith, L. K. Mathew, V. A. Prasad, and S. A. Fahmy
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 6, pp. 1183–1191, June 2018.

• Smart Network Interfaces for Advanced Automotive Applications
  S. Shreejith and S. A. Fahmy
  IEEE Micro, vol. 38, no. 2, pp. 72–80, March/April 2018.

• A Time-Multiplexed FPGA Overlay with Linear Interconnect
  X. Li, A. K. Jain, D. L. Maskell and S. A. Fahmy
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2018. pp. 1075–1080.

2017

• An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration
  T. H. Pham, S. A. Fahmy, and I. V. McLoughlin
  IEEE Access, vol. 5, pp. 21002–20015, 2017.

• VEGa: A High Performance Vehicular Ethernet Gateway on Hybrid FPGA
  S. Shreejith, P. Mundhenk, A. Ettner, S. A. Fahmy, S. Steinhorst, M. Lukasiewycz, and S. Chakraborty
  IEEE Transactions on Computers, vol. 66 no. 10, pp. 1790–1803, October 2017.

• Multi-pumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs
  B. Ronak and S. A. Fahmy
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 36, no. 9, pp. 1471–1482, September 2017.

• Fracturable DSP Block for Multi-context Reconfigurable Architectures
  R. Warrier, S. Shreejith, W. Zhang C. H. Vun, and S. A. Fahmy
  Circuits, Systems, and Signal Processing, vol. 36, no. 7, pp. 3020–3033, July 2017, Springer.

• Metrics for Energy-Aware Software Optimisation
  S. I. Roberts, S. A. Wright, S. A. Fahmy, S. A. Jarvis
  Proceedings of ISC High Performance (formerly International Supercomputing Conference), Frankfurt Germany, June 2017, pp. 413–440.

• Security in Automotive Networks: Lightweight Authentication and Authorization
  P. Mundhenk, A. Paverd, A. Mrowca, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, and S. Chakraborty
  ACM Transactions on Design Automation of Electronic Systems, vol. 22, no. 2, pp. 25:1–25:27, March 2017.
  ACM TODAES 2019 Best Paper Award Winner

• Virtualized Execution Runtime for FPGA Accelerators in the Cloud
  M. Asiatici, N. George, K. Vipin, S. A. Fahmy, and P. Ienne
  IEEE Access, vol. 5, pp. 1900–1910, 2017.

2016

• A Power and Time Efficient Radio Architecture for LDACS1 Air-to-Ground Communication
  S. Shreejith, A. Ambede, A. P. Vinod, and S. A. Fahmy
  Proceedings of the Digital Avionics Systems Conference (DASC), Sacramento, CA, September 2016.

• JetStream: An Open-Source High-Performance PCI Express 3 Streaming Library for FPGA-to-Host and FPGA-to-FPGA Communication
  M. Vesper, D. Koch, K. Vipin, and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 2016.
  FPL 2016 Community Award Winner

• Improved Resource Sharing for FPGA DSP Blocks
  B. Ronak and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 2016.

• Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
  A. K. Jain, D. L. Maskell, and S. A. Fahmy
  Proceedings of the IEEE International Conference on Pervasive, Intelligence and Computing (PICom), Auckland, New Zealand, August 2016, pp. 586–593.

• Open Source Model and Simulator for Real-Time Performance Analysis of Automotive Network Security
  P. Mundhenk, A. Mrowca, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, S. Chakraborty
  ACM SIGBED Review, vol. 13, no. 3, pp. 8-13, June 2016.

• DeCO: A DSP Block Based FPGA Accelerator Overlay With Low Overhead Interconnect
  A. K. Jain, D. L. Maskell, and S. A. Fahmy
  Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Washington, DC, May 2016, pp. 1–8.

• Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization
  T. H. Pham, S. A. Fahmy, and I. V. McLoughlin
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1412–1420, April 2016.

• Mapping for Maximum Performance on FPGA DSP Blocks
  B. Ronak and S. A. Fahmy
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 35, no. 4, pp. 573–585, April 2016.

• Spectrally Efficient Emission Mask Shaping for OFDM Cognitive Radios
  T. H. Pham, S. A. Fahmy, and I. V. McLoughlin
  Digital Signal Processing, vol. 50, pp. 150–161, March 2016, Elsevier.

• Throughput Oriented FPGA Overlays Using DSP Blocks
  A. K. Jain, D. L. Maskell, and S. A. Fahmy
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016, pp. 1628–1633.

• Accelerated Artificial Neural Networks on FPGA for Fault Detection in Automotive Systems
  S. Shreejith, B. Anshuman, and S. A. Fahmy
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016, pp. 37–42.

• Design and Realization of Variable Digital Filters for Software Defined Radio Channelizers using Improved Coefficient Decimation Method
  A. Ambede, S. Shreejith, A. P. Vinod, and S. A. Fahmy
  IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 1, pp. 59–63, January 2016.

2015

• JIT Trace-Based Verification for High-Level Synthesis
  L. Yang, M. Ikram, S. Gurumani, S. A. Fahmy, D. Chen, and K. Rupnow
  Proceedings of the International Conference on Field Programmable Technology (FPT), Queenstown, New Zealand, December 2015, pp. 228–231.

• Minimising DSP Block Usage Through Multi-Pumping
  B. Ronak and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), Queenstown, New Zealand, December 2015, pp. 184–187.

• Virtualized FPGA Accelerators for Efficient Cloud Computing
  S. A. Fahmy, K. Vipin, and S. Shreejith
  Proceedings of the IEEE International Conference on Cloud Computing Technology and Science (CloudCom), Vancouver, Canada, November 2015, pp. 430–435.

• Mapping Adaptive Hardware Systems with Partial Reconfiguration Using CoPR for Zynq
  K. Vipin and S. A. Fahmy
  Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Montreal, Canada, June 2015.

• Security Aware Network Controllers for Next Generation Automotive Embedded Systems
  S. Shreejith and S. A. Fahmy
  Proceedings of the Design Automation Conference (DAC), San Francisco, CA, June 2015, pp. 39:1–39:6.

• Security Analysis of Automotive Architectures using Probabilistic Model Checking
  P. Mundhenk, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, and S. Chakraborty
  Proceedings of the Design Automation Conference (DAC), San Francisco, CA, June 2015, pp. 38:1–38:6.

• Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq
  A. K. Jain, X. Li, S. A. Fahmy, and D. L. Maskell
  Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Boston, MA, June 2015.

• Efficient Overlay Architecture Based on DSP Blocks
  A. K. Jain, S. A. Fahmy, and D. L. Maskell
  Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Vancouver, Canada, May 2015, pp. 25–28.

• Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA
  S. Shreejith, B. Banarjee, K. Vipin, and S. A. Fahmy
  Proceedings of the International Conference on Cognitive Radio Oriented Wireless Networks (CROWNCOM), Doha, Qatar, April 2015, pp. 427–437.

• Lightweight Authentication for Secure Automotive Networks
  P. Mundhenk, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, and S. Chakraborty
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Grenoble, France, March 2015, pp. 285–288.

• On Data Forwarding in Deeply Pipelined Soft Processors
  H. Y. Cheah, S. A. Fahmy, and N. Kapre
  Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2015, pp. 181–189.

• Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems
  S. Shreejith and S. A. Fahmy
  IEEE Transactions on Vehicular Technology, vol. 64, no. 2, pp. 453–465, February 2015.

2014

• Zero Latency Encryption with FPGAs for Secure Time-Triggered Automotive Networks
  S. Shreejith and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), Shanghai, China, December 2014, pp. 256–259.

• Analysis and Optimization of a Deeply Pipelined FPGA Soft Processor
  H. Y. Cheah, S. A. Fahmy, and N. Kapre
  Proceedings of the International Conference on Field Programmable Technology (FPT), Shanghai, China, December 2014, pp. 235–238.

• System Simulation and Optimization using Reconfigurable Hardware
  M. Lukasiewycz, S. Shreejith, and S. A. Fahmy
  Proceedings of the International Symposium on Integrated Circuits (ISIC), Singapore, December 2014, pp. 468–471.

• Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform
  A. K. Jain, K. D. Pham, J. Cui, S. A. Fahmy, and D. L. Maskell
  Journal of Signal Processing Systems, vol. 77, no. 1-2, pp. 61–76, October 2014, Springer.

• DyRACT: A Partial Reconfiguration Enabled Accelerator and Test Platform
  K. Vipin and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014.

• Efficient Mapping of Mathematical Expressions into DSP Blocks
  B. Ronak and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014.

• ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq
  K. Vipin and S. A. Fahmy
  IEEE Embedded Systems Letters, vol. 6, no. 3, pp. 41–44, September 2014.

• Mapping Time-Critical Safety-Critical Systems to Hybrid FPGAs
  K. Vipin, S. Shreejith, S. A. Fahmy, and A. Easwaran
  Proceedings of the IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA), Hong Kong, China, August 2014, pp. 31–36.

• A Case for Leveraging 802.11p for Direct Phone-to-Phone Communications
  P. Choi, J. Gao, N. Ramanathan, M. Mao, S. Xu, C. C. Boon, S. A. Fahmy, and L. S. Peh
  Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA, August 2014, pp. 207–212.

• The iDEA DSP Block Based Soft Processor for FPGAs
  H. Y. Cheah, F. Brosser, S. A. Fahmy, and D. L. Maskell
  ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 3, Article 19, August 2014.

• Robust and Efficient OFDM Synchronisation for FPGA-Based Radios
  T. H. Pham, I. V. McLoughlin, and S. A. Fahmy
  Circuits, Systems, and Signal Processing, vol. 33, no. 8, pp. 2475–2493, August 2014, Springer.

• Shaping Spectral Leakage for IEEE 802.11p Vehicular Communications
  T. H. Pham, I. V. McLoughlin, and S. A. Fahmy
  Proceedings of the IEEE Vehicular Technology Conference (VTC Spring), Seoul, Korea, May 2014.

• Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq
  K. Vipin and S. A. Fahmy
  Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014, pp. 202–205.

• Square-Rich Fixed Point Polynomial Evaluation on FPGAs
  S. Xu, S. A. Fahmy, and I. V. McLoughlin
  Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2014, pp. 99–108.

2013

• Accelerating Validation of Time-Triggered Automotive Systems on FPGAs S. Shreejith, S. A. Fahmy, and M. Lukasiewycz
  Proceedings of the International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013, pp. 4–11.
  FPT 2013 Best Paper Nominee

• System-Level FPGA Device Driver with High-Level Synthesis Support
  K. Vipin, S. Shreejith, D. Gunasekara, S. A. Fahmy, and N. Kapre
  Proceedings of the International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013, pp. 128–135.

• Optimization of the HEFT algorithm for a CPU-GPU environment
  K. R. Shetti, S. A. Fahmy, and T. Bretschneider
  Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies, Taipei, Taiwan, December 2013, pp. 212–218.

• Iterative Floating Point Computation Using FPGA DSP Blocks
  F. Brosser, H. Y. Cheah, and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, September 2013.

• Low-Power Correlation for IEEE 802.16 OFDM Synchronisation on FPGA
  T. H. Pham, S. A. Fahmy, and I.V. McLoughlin
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 8, pp. 1549–1553, August 2013.

• System Architecture and Software Design for Electric Vehicles
  M. Lukasiewycz, S. Steinhorst, S. Andalam, F. Sagstetter, P. Waszecki, W. Chang, M. Kauer, P. Mundhenk, S. Shreejith, S. A. Fahmy, S. Chakraborty
  Proceedings of the Design Automation Conference (DAC), Austin, TX, June 2013, Article 95.

• Microkernel Hypervisor for a Hybrid ARM-FPGA Platform
  K. D. Pham, A. K. Jain, J. Cui, S. A. Fahmy, and D. L. Maskell
  Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, June 2013, pp. 219–226.

• Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems
  K. Vipin and S. A. Fahmy
  Proceedings of the Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW) – Reconfigurable Architectures Workshop (RAW), Boston, MA, May 2013, pp. 172–181.

• Architecture for Real-Time Nonparametric Probability Density Function Estimation
  S. A. Fahmy and A. R. Mohan
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 5, pp. 910–920, May 2013.

• Efficient Large Integer Squarers on FPGA
  S. Xu, S. A. Fahmy, and I. V. McLoughlin
  Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Seattle, WA, April 2013, pp. 198–201.

• An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration
  S. Shreejith, K. Vipin, S. A. Fahmy, and M. Lukasiewycz
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Grenoble, France, March 2013, pp. 721–724.

• Reconfigurable Computing in Next-Generation Automotive Networks
  S. Shreejith, S. A. Fahmy, and M. Lukasiewycz
  IEEE Embedded Systems Letters, vol. 5, no. 1, pp. 12–15, March 2013.

2012

• iDEA: A DSP Block Based FPGA Soft Processor
  H. Y. Cheah, S. A. Fahmy, and D. L. Maskell
  Proceedings of the International Conference on Field Programmable Technology (FPT), Seoul, Korea, December 2012, pp. 151–158.
  FPT 2012 Best Paper Award Winner

• A High Speed Open Source Controller for FPGA Partial Reconfiguration
  K. Vipin and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), Seoul, Korea, December 2012, pp. 61–66.

• Evaluating the Efficiency of DSP Block Synthesis Inference from Flow Graphs
  B. Ronak and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 2012, pp. 727–730.

• Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration
  K. Vipin and S. A. Fahmy
  Reconfigurable Computing: Architectures, Tools and Applications – Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), Hong Kong, March 2012, pp. 13–25.

• Embedded Systems and Software Challenges in Electric Vehicles
  S. Chakraborty, M. Lukasiewycz, C. Buckl, S. A. Fahmy, N. Chang, S. Park, Y.Kim, P. Leteinturier, and H. Adlkofer
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2012, pp. 424–429.

• A Lean FPGA Soft Processor Built Using a DSP Block
  H. Y. Cheah, S. A. Fahmy, D. L. Maskell, and C. Kulkarni
  Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2012, pp. 237–240.

2011

• Efficient Region Allocation for Adaptive Partial Reconfiguration
  K. Vipin and S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), New Delhi, India, December 2011.

• A Model-Based Approach to Cognitive Radio Design
  J. Lotze, S. A. Fahmy, J. Noguera, and L.E. Doyle
  IEEE Journal on Selected Areas in Communications (JSAC), vol. 29, no. 2, pp. 455–468, February 2011.

2010

• Histogram-Based Probability Density Function Estimation on FPGAs
  S. A. Fahmy
  Proceedings of the International Conference on Field Programmable Technology (FPT), Beijing, China, December 2010, pp. 449–453.

• Iris – An Architecture for Cognitive Radio Networking Testbeds
  P. D. Sutton, J. Lotze, H. Lahlou, S. A. Fahmy, K.E. Nolan, B. Özgül, T. W. Rondeau, J. Noguera, and L.E. Doyle
  IEEE Communications Magazine, vol. 48, no. 9, pp. 114–122, September 2010.

• Multi-Platform Demonstrations using the Iris Architecture for Cognitive Radio Network Testbeds
  P. D. Sutton, J. Lotze, H. Lahlou, B. Özgül, S. A.Fahmy, K. E. Nolan, J. Noguera, and L. E.Doyle
  Proceedings of the International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CrownCom), Cannes, France, June 2010.

• Experiences from the Iris Testbed in Dynamic Spectrum Access and Cognitive Radio Experimentation
  L. E. Doyle, P. D. Sutton, K. E. Nolan, J. Lotze, B. Özgül, T. W. Rondeau, S. A. Fahmy, H. Lahlou, and L. A. Dasilva
  Proceedings of the IEEE Symposia on New Frontiers in Dynamic Spectrum Access Networks (DySPAN), Singapore, April 2010.

• Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing
  S. A. Fahmy and L. E. Doyle
  Reconfigurable Computing: Architectures, Tools and Applications – Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), Bangkok, Thailand, March 2010, pp. 343–350.

2009

• Spectrum Sensing on LTE Femtocells for GSM Spectrum Re-Farming Using Xilinx FPGAs
  J. Lotze, S. A. Fahmy, J. Noguera, B. Ozgül, and L. Doyle
  Proceedings of the Software-Defined Radio Forum Technical Conference (SDR Forum), Washington, DC, December 2009.

• Development Framework for Implementing FPGA-Based Cognitive Network Nodes
  J. Lotze, S. A. Fahmy, J. Noguera, B. Ozgül, L. Doyle, and R. Esser
  Proceedings of the IEEE Global Communications Conference (GLOBECOM), Honolulu, Hawaii, December 2009.

• High-Throughput One-Dimensional Median and Weighted Median Filters on FPGA
  S. A. Fahmy, P. Y. K. Cheung, and W. Luk
  IET Computers and Digital Techniques (IET-CDT), vol. 3, no. 4, pp. 384–394, July 2009.

• Generic Software Framework for Adaptive Systems on FPGAs
  S. A. Fahmy, J. Lotze, J. Noguera, L. Doyle, and R. Esser
  Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Napa, CA, April 2009, pp. 55–62.

2008

• Generalised Parallel Bilinear Interpolation Architecture for Vision Systems
  S. A. Fahmy
  Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 2008, pp. 331–336.

• An FPGA-based Cognitive Radio Framework
  J. Lotze, S. A. Fahmy, J. Noguera, L. Doyle, and R. Esser
  Proceedings of the IET Irish Signals and Systems Conference (ISSC), Galway, Ireland, June 2008, pp. 138–143.

2007

• Real-Time Hardware Acceleration of the Trace Transform
  S. A. Fahmy, C. -S. Bouganis, P. Y. K. Cheung, and W. Luk
  Journal of Real-Time Image Processing, vol. 2, no. 4, pp. 235–248, December 2007, Springer.

2006

• Efficient Realtime FPGA Implementation of the Trace Transform
  S. A. Fahmy, C. -S. Bouganis, P. Y. K. Cheung, and W. Luk
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006, pp. 555–560.

2005

• Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing
  S. A. Fahmy, P. Y. K. Cheung, and W. Luk
  Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 2005, pp. 142–147.

• Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
  S. A. Fahmy, P. Y. K. Cheung, and W. Luk
  Proceedings of the Design, Automation and Test in Europe Conference (DATE), Munich, Germany, March 2005, pp. 8–13.

Posters, Reports, and Demonstrations

• Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design
  M. Bouaziz and S. A. Fahmy
  PhD Forum Paper in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), Hong Kong, July 2024.

• Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload
  E. Grindley, T. Gray, J. Wilkinson, C. Vaux, A. Ardron, J. Deeley, A. Elliott, N. T. Sumithran, and S. A. Fahmy
  Poster in Proceedings of the International Conference on Field Programmable Technology (FPT), Yokohama, Japan, December 2023.

• Exploring FPGA Acceleration for Distributed Serverless Computing
  Z. Yang and S. A. Fahmy
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Gothenburg, Sweden, September 2023.

• Neural Network Overlay Using FPGA DSP Blocks
  L. Ioannou and S. A. Fahmy
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September 2019.

• In-network online data analytics with FPGAs
  R. Cooke and S. A. Fahmy
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, September 2017.

• Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays
  A. K. Jain, D. L. Maskell, S. A. Fahmy
  Workshop Paper at the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017), Monterey, CA, February 2017.

• Designing a Virtual Runtime for FPGA Accelerators in the Cloud
  M. Asiatici, N. George, K. Vipin, S. A. Fahmy, and P. Ienne
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 2016.

• Initiation Interval Aware Resource Sharing for FPGA DSP Blocks
  B. Ronak and S. A. Fahmy
  Poster in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Washington, DC, May 2016.

• An Area-Efficient FPGA Overlay Using DSP Block Based Time-Multiplexed Functional Units
  X. Li, A. K. Jain, D. L. Maskell, and S. A. Fahmy
  Workshop Paper at the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016), Monterey, CA, February 2016.

• Automated Verification Code Generation in HLS Using Software Execution Traces
  L. Yang, S. T. Gurumani, S. A. Fahmy, D. Chen, and K. Rupnow Poster in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2016, pp. 278.

• A Case for FPGA Accelerators in the Cloud
  S. A. Fahmy and K. Vipin
  Poster at ACM Symposium on Cloud Computing (SoCC), Seattle, WA, November 2014.

• Efficient Multi-Standard Cognitive Radios on FPGAs
  T. H. Pham, S. A. Fahmy, and I. V. McLoughlin
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014.

• A Scalable and Compact Systolic Architecture for Linear Solvers
  K. S. H. Ong, S. A. Fahmy, and K.-V. Ling
  Poster in Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, June 2014, pp. 186–187.

• Experiments in Mapping Expressions to DSP Blocks
  B. Ronak and S. A. Fahmy
  Poster in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014, pp. 101.

• Enhancing Communication On Automotive Networks Using Data Layer Extensions
  S. Shreejith and S. A. Fahmy
  Demonstration Paper in Proceedings of the International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013, pp. 470–473.

• An Approach to a Fully Automated Partial Reconfiguration Design Flow
  K. Vipin and S. A. Fahmy
  Poster in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Seattle, WA, April 2013, pp. 231.

• Enabling High Level Design of Adaptive Systems with Partial Reconfiguration
  K. Vipin and S. A. Fahmy
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Technology (FPT), New Delhi, India, December 2011.

• A Threat Based Connect6 Implementation on FPGA
  K. Vipin and S. A. Fahmy
  Design Competition Paper in Proceedings of the International Conference on Field Programmable Technology (FPT), New Delhi, India, December 2011.

• An FPGA-Based Autonomous Adaptive Radio
  J. Lotze, S. A. Fahmy, J. Noguera, and L. Doyle
  Demonstration Poster, ACM SIGCOMM, Barcelona, Spain, August 2009.

• Spectrum Sensing to Achieve Frequency Rendezvous using Xilinx FPGAs
  J. Lotze, B. Ozgül, S. A. Fahmy, J. Noguera, L. Doyle, and R. Esser
  Demonstration at IEEE Symposia on New Frontiers in Dynamic Spectrum Access Networks (DySPAN), Chicago, Illinois, October 2008.

• High-level Cognitive Radio Design Using Xilinx FPGAs
  J. Lotze, S. A. Fahmy, J. Noguera, L. Doyle, and R. Esser
  Demonstrated at Collaborative International Software Defined Radio Workshop (CISDR), Maynooth, Ireland, May 2008.

• Investigating Trace Transform Architectures for Face Authentication
  S. A. Fahmy
  PhD Forum Paper in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006, pp. 929–930.

Book Chapters

• Dynamic and Partial Reconfiguration of FPGAs
  S. A. Fahmy and K. B. Iyer
  In Handbook of Computer Architecture, Springer Nature, 2024.

• From Algorithms to Hardware Implementation
  C. -S. Bouganis, S. A. Fahmy, and P. Y. K. Cheung
  In Next Generation Artifical Vision Systems: Reverse Engineering the Human Visual System, A. Bharath and M. Petrou Eds., 2008, pp. 367–393.

PhD Thesis

• S. A. Fahmy “Hardware Acceleration of the Trace Transform for Vision Applications” PhD Thesis, Imperial College London, University of London, UK, 2007.

Previous Students' Theses

At University of Warwick, UK

• Machine Learning at the Edge for Air Quality Prediction
  I Nyoman Kusuma Wardana (co-supervised with Julian Gardner), PhD, University of Warwick, 2024, now at Politeknik Negeri Bali

• High-Level FPGA Accelerator Design for Structured-Mesh-Based Numerical Solvers
  Kamalavasan Kamalakkannan (co-supervised with Gihan Mudalige), PhD, University of Warwick, 2023, now at Los Alamos National Laboratory

• Build Framework and Runtime Abstraction for Partial Reconfiguration on FPGA SoCs
  Alex Bucknall, PhD, University of Warwick, 2022, now at Blues

• Exploring the Capabilities of FPGA DSP Blocks in Neural Network Accelerators
  Lenos Ioannou, PhD, University of Warwick, 2022, now at SignalGenerix

• An Applications Approach to Benchmarking and Performance Modelling Low Latency Interconnection Networks
  Dean Chester (co-supervised with Stephen Jarvis and Gihan Mudalige), PhD, University of Warwick, 2021, now at Cornelis Networks

• Modelling and Characterisation of Distributed Hardware Acceleration
  Ryan Cooke, PhD, University of Warwick, 2020, now at Balena.io

• Energy Aware Performance Engineering in High Performance Computing
  Stephen Roberts (co-supervised with Stephen Jarvis), PhD, University of Warwick, 2018, now at Google

At NTU Singapore

• Security for Automotive Electrical/Electronic (E/E) Architectures
  Philipp Mundhenk (co-supervised with Samarjit Chakraborti), PhD, TU Munich and NTU Singapore, 2017, now at Bosch

• Architecture Centric Coarse-Grained FPGA Overlays
  Abhishek Jain (co-supervised with Douglas Maskell), PhD, NTU Singapore, 2017, now at AMD

• Exploiting DSP Block Capabilities in FPGA High Level Design Flows
  Ronak Bajaj, PhD, NTU Singapore, 2016 now at Marvell

• The iDEA Architecture-Focused FPGA Soft Processor
  Hui Yan Cheah (co-supervised with Nachiket Kapre), PhD, NTU Singapore, 2016, now at AMD

• Enhancing Automotive Embedded Systems with FPGAs
  Shreejith Shanker, PhD, NTU Singapore and TU Munich, 2016, now at Trinity College Dublin

• Techniques for Multi-Standard Cognitive Radios on FPGAs
  Hung Thinh Pham (co-supervised with Ian McLoughlin), PhD, NTU Singapore, 2015, now at Arm

• Design Automation for Partially Reconfigurable Adaptive Systems
  Vipin Kizheppatt, PhD, NTU Singapore, 2015, now at BITS Pilani Goa

• A Scalable and Compact Linear Solver with a Focus on Model Predictive Control
  Kevin Ong, MEng, NTU Singapore, 2014, now at Bosch

• Optimization and Scheduling of Applications in a Heterogeneous CPU-GPU Environment
  Karan Shetti, MEng, NTU Singapore, 2014, now at Aptiv

• Embedded Virtualization of a Hybrid ARM-FPGA Computing Platform
  Khoa Pham (co-supervised with Douglas Maskell), MEng, NTU Singapore, 2014, now at AMD

• Efficient Polynomial Evaluation Algorithm and Implementation on FPGA
  Simin Xu, MEng, NTU Singapore, 2013, now at AMD

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